Non-volatile memory (“NVM”) refers to semiconductor memory which is able to continually store information even when the supply of electricity is removed from the device containing the NVM cell. NVM includes Mask Read-Only Memory (Mask ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), and Flash Memory. Non-volatile memory is extensively used in the semiconductor industry and is a class of memory developed to prevent loss of programmed data. Typically, non-volatile memory can be programmed, read and/or erased based on the device's end-use requirements, and the programmed data can be stored for a long period of time.
Non-volatile memory devices can employ various designs, including devices which have charge storage layers of the “floating gate” type and devices which have charge-trapping layers that store charge in a localized manner. Localized charge storage (or trapping) refers to the ability of a charge-trapping layer to store charge without significant lateral movement of the stored charge throughout the layer. Conventional “floating gate” memory cells contain a charge-storage layer which is conductive and in which the stored charge is spread laterally throughout the entire layer (i.e., throughout the entire floating gate).
As the information technology market has grown vastly in the past twenty years or so, portable computers and the electronic communications industry have become the main driving force for semiconductor VLSI (very large scale integration) and ULSI (ultra large scale integration) design. As a result, low power consumption, high density and re-programmable non-volatile memory are in great demand. These types of programmable and erasable memories have become essential devices in the semiconductor industry.
A rising demand for memory capacity has translated into higher requirements for integration level and memory density. Dual bit cells which can store two bits of information in each memory cell are known in the art but are not yet prevalent in use. Some dual bit cells have multiple threshold voltage levels, where every two threshold voltage levels together store a different bit. These types of dual bit cells involve operational complexities which discourage their widespread use. Other dual bit cells employ charge-trapping layers and have two separate storage sites and store one bit in each site on either side of the cell. One kind of dual bit cell of the latter variety is known as Nitride Read Only Memory (NROM).
In general, an NROM cell uses a thicker tunnel oxide layer between the semiconductor layer and the charge-trapping nitride layer to prevent charge loss during retention states. However, a thick tunnel oxide layer may impact channel erase speed. As a result, band-to-band tunneling hot-hole (BTBTHH) erase methods are often used to inject hole traps from the channel to compensate the stored electrons. However, the BTBTHH erase methods may cause reliability issues. For example, the performance characteristics of NVM devices employing BTBTHH erase methods may rapidly degrade after numerous P/E (program/erase) cycles due to semiconductor layer/oxide interface damage which can occur as a result of the BTBTHH methods. For purposes of this invention, the “semiconductor layer” refers to that layer in which the source/drain regions are proximate to the layer's surface and the “semiconductor substrate” or “substrate” refers to a support or insulation layer contiguous to the semiconductor layer that does not contain source/drain regions. Not all semiconductor devices have semiconductor substrates and in those instances the semiconductor layer is commonly considered to also be the substrate.
Another example of a charge-trapping NVM cell design is the so-called SONOS (silicon-oxide-nitride-oxide-silicon) device, which can include a thin tunnel oxide layer between the semiconductor layer and the charge-trapping layer to allow hole direct tunneling erase operations. Although such designs can have good erase speed, the data retention is usually poor, in part, because direct tunneling may occur even at a low electrical field strengths that may exist during a retention state of a memory device.
Thus, a need in the art exists for non-volatile memory cell designs and arrays which can be repeatedly programmed and erased numerous times with improved data retention performance, increased operation speeds and which do not suffer semiconductor layer/oxide interface degradation as a result of hot hole tunneling from the semiconductor layer.